Luca Cassano

Luca Cassano

Bio

Luca Cassano is an Assistant Professor at Politecnico di Milano, Italy. He received the BS, MS and PhD degrees in computer engineering from the University of Pisa, Italy. His research activity focuses on the definition of innovative techniques for fault simulation, testing, untestability analysis, diagnosis, and verification of fault tolerant and secure digital circuits and systems. With his PhD thesis, titled “Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs”, he won the European semifinals of the 2014 TTTC’s E. J. McCluskey Doctoral Thesis Award and he classified as runner-up at the world finals.